Jason Frederick Cantin
3401 Parmer Lane West #1321
Austin, Texas 78727



Education:

	University of Wisconsin, Madison, Wisconsin.
           PhD 2006, Computer Engineering, Minor in Computer Science.
           MSEE 2002, Computer Engineering.

	University of Cincinnati, Cincinnati, Ohio.
           BSEE 2000, Electrical Engineering, Minor in VLSI Design.
           BSCompE 2000, Computer Engineering, Minor in Mathematics.
           Cumulative GPA: 3.82 / 4.00 (Magna Cum Laude).


Issued Patents:

        #6,960,941: "Latch Circuit Capable of Ensuring Race-Free Staging for Signals
         in Dynamic Logic Circuits", 2004.

        #6,107,839: "High Input Impedance, Strobed CMOS Differential Sense Amplifier
         with Double-Fire Evaluate", 2000.


Selected Publications:

        J. F. Cantin, A. Moshovos, M. H. Lipasti, J. E. Smith, and B. Falsafi,
        "Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays", 
        IEEE Micro Special Issue on Top Picks from 2005 Computer Architecture
        Conferences, Jan-Feb 2006.

        J. F. Cantin, M. H. Lipasti, and J. E. Smith, "The Complexity of Verifying
        Memory Coherence and Consistency", IEEE Transactions on Parallel and 
        Distributed Systems, Volume 16, No. 7, July 2005.

        J. F. Cantin, M. H. Lipasti, and J. E. Smith, "Improving Multiprocessor
        Performance with Coarse-Grain Coherence Tracking", International Symposium
        on Computer Architecture, June 2005.

        J. F. Cantin and M. D. Hill, "Cache Performance for Selected SPEC CPU2000
        Benchmarks", Computer Architecture News, Vol. 29, No. 4, September 2001.

        P. Mal, J. F. Cantin and F. R. Beyette Jr., "Design and Demonstration of an
        Optical Field Programmable Gate Array", SPIE Annual Meeting, August 2001.

        J. F. Cantin and F. R. Beyette Jr., "Design and Evaluation of a Configurable
        Architecture for Smart Pixel Research", Optical Computing Conference, 
        January 2001.     


Work Experience:

        International Business Machines, Austin, Texas.
           Advisory Engineer, Server Hardware / HPC Performance, June 2006 to present.

            Invent, research, and develop techniques for improving the 
            performance, scalability, and efficiency of memory subsystem 
            hardware for servers and High-Performance Computing initiatives.

        International Business Machines, Rochester, Minnesota.
           Intern, eServer Hardware Performance Group, July 2005 to October 2005.

            Evaluated potential for Coarse-Grain Coherence Tracking in a future
            system design.

            Proposed and evaluated cache replacement algorithm optimizations.

            Developed trace conversion tools for memory subsystem simulation.

        International Business Machines, Austin, Texas.
           Intern, eServer Hardware Performance Group, August 2004 to December 2004.

            Proposed and evaluated coherence protocol optimizations to improve
            memory system performance and scalability (patents pending).

            Proposed new memory prefetching techniques.

        International Business Machines, Austin, Texas.
           Intern, eServer Hardware Performance Group, May 2003 to August 2003.

            Proposed and evaluated coherence protocol optimizations to improve
            memory system performance and scalability (patents pending).

            Evaluated prefetching in the memory system.

            Developed new latch design for asynchronous, race-free staging of
            signals (patent filed).

        Compaq Computer Corporation, Cambridge, Massachusetts.
	   Intern, Cambridge Research Laboratory, June 2000 to August 2000.

            Developed low-power analog circuitry for personal digital assistants.

            Designed and prototyped precision current measurement instruments for
            use in prototyping and development.

            Studied the characteristics of Lithium batteries under static and
            dynamic workloads.

            Created LabView virtual instruments to characterize battery performance 
            for feasibility.

            Interacted directly with vendors and product engineers from other 
            companies to obtain component samples and evaluate the availability of 
            components for production.
     
        Compaq Computer Corporation, Shrewsbury, Massachusetts.
           Co-op, Alpha Development Group, March 1999 to September 1999.

            Developed microarchitectural specifications of Alpha 21464 I/O handling 
            circuits.

            Created SPICE simulations, size estimates, wiring diagrams, floorplans,
            and documentation for I/O handling circuits.

            Produced schematics for the I/O handling section.
                        
            Simulated critical paths in advanced, deep-submicron SOI CMOS fabrication
            technologies.
                        
            Developed tools for latch performance evaluation.
                
        Digital Equipment Corporation / Compaq, Shrewsbury Massachusetts
           Co-op, Alpha Development Group, March 1998 to September 1998.
                        
            Researched, designed, and characterized latches.
                        
            Developed and maintained automated latch characterization tools.
                        
            Created block diagrams for Alpha 21464 translation buffers.

            Developed circuit techniques for improving the sensitivity of CMOS 
            differential sense amplifiers (U.S. Patent #6,107,839).
                        
            Researched TLB sizes, associativities, replacement, and circuit 
            feasibility.

        Digital Equipment Corporation, Hudson, Massachusetts.
           Co-op, Alpha Development Group, March 1997 to September 1997.
                        
            Researched, designed, and characterized latches.
                        
            Developed automated latch characterization tools.
                        
            Performance modeling and code instrumentation.
                        
            Investigated impact of floating-point lookup-table sizes on overall 
            performance in the Alpha 21464.
                        
            Researched and evaluated L1-cache replacement policies.

                          
Computer Skills:

        High-Level Languages:  	C, C++, Java, Pascal, Visual Basic, VHDL, Verilog,
                              	FORTRAN.

        Scripting Languages:  	Tcsh, Ksh, Perl, RPL.

        Assembly Languages:   	Alpha, MIPS, Sparc V9, PowerPC, MC68000.

        Operating Systems:     	Tru64 Unix, Solaris, AIX, Redhat Linux, MS-DOS, 
                                OpenVMS, WindowsXP/2000/NT/98/95.
					 
        Software Development:  	Lex, Yacc, Emacs, VI, JBuilder, MS Visual Studio.

        Design Software:       	Matlab, Simulink, PSPICE, SPICE, Magic, IRSIM, 
                                B^2 Logic, LabVIEW 5.0, Mathematica, MathCAD, 
                                Espresso, Altera MAX II Plus, Viewlogic, NuSMV,
                                Simplescalar 3.0.

        Business Software:      Microsoft Office, Visio, Latex, Gnuplot, Lotus 
                                SmartSuite.


Awards:

        IBM Graduate Research Fellowship, 2004-2006.
        National Science Foundation Graduate Research Fellowship, 2001-2004.
        University of Wisconsin Distinguished Graduate Fellowship, 2000-2001.
        Best Senior Project Award, University of Cincinnati, 2000.
        George Donald Moon Scholarship Award, Triangle, 2000.
        Thomas Kirby Scholarship, University of Cincinnati, 1999.
        Charles Constable Scholarship, University of Cincinnati, 1996.


Professional Affiliations:

        Association for Computing Machinery (ACM).
        Institute for Electrical and Electronics Engineers (IEEE).