Patents and Publications:
- Papers published in peer-reviewed journals:
- J. F. Cantin, M. H. Lipasti, and J. E. Smith, "The Complexity of Verifying
Memory Coherence and Consistency", IEEE Transactions on Parallel and
Distributed Systems (IEEE TPDS), Vol. 16, No. 7, July 2005.
- Conference papers:
- N. Aggarwal, J. F. Cantin, M. H. Lipasti, and J. E. Smith, "Power-Efficient
DRAM Speculation", Fourteenth International Symposium on High-Performance
Computer Architecture (HPCA), February 2008. (pdf)
- J. F. Cantin, M. H. Lipasti, and J. E. Smith, "Stealth Prefetching", Twelfth
International Conference on Architectural Support for Programming Languages
and Operating Systems (ASPLOS), October 2006. (pdf)
- J. F. Cantin, M. H. Lipasti, and J. E. Smith, "Improving Multiprocessor
Performance with Coarse-Grain Coherence Tracking", International
Symposium on Computer Architecture (ISCA), June 2005. (pdf)
- P. Mal, J. F. Cantin, S. Kumar, A. Pattanyak and F.R. Beyette, Jr,
"Programmable Photoreceiver Module for Incorporation in an Optical Field
Programmable Gate Array", SPIE ITCOM, Denver CO, Aug 2001.
Proceedings due March 2002.
- P. Mal, J. F. Cantin, and Fred R. Beyette, Jr., "Design and Demonstration
of a Configurable Architecture for Smart Pixel Research", IEEE Midwest
Symposium on Circuits and Systems, Dayton OH, Aug 2001, pp. 405-408.
- P. Mal, J. F. Cantin and F. R. Beyette Jr., "Design and Demonstration of an
Optical Field Programmable Gate Array", SPIE Annual Meeting,
San Diego CA, August 2001. Proceedings due March 2002.
- J. F. Cantin and F. R. Beyette Jr., "Design and Evaluation of a Configurable
Architecture for Smart Pixel Research", Optical Computing Conference,
Jan 2001, Lake Tahoe NV, pp. 5-7.
- J. F. Cantin and F. R. Beyette Jr., "Design and Evaluation of a Field
Programmable Smart Pixel Array with Programmable Photoreceivers", Optical
Computing Conference, Jan 2001, Lake Tahoe NV, pp. 102-104.
- J. F. Cantin and F. R. Beyette, "A Configurable Architecture for Smart Pixel
Research" Proceedings of the IEEE/LEOS Summer Topical Meeting on
Electronics-Enhanced Optics, pp. 67-68, July 2000
- Workshop papers:
- J. F. Cantin, M. H. Lipasti, J. E. Smith, "Dynamic Verification of Cache
Coherence Protocols" 2001 ISCA Workshop on Memory Performance Issues (WMPI),
June 2001. (pdf)
- J. F. Cantin, M. H. Lipasti, and J. E. Smith, "The Complexity of Verifying
Memory Coherence", Symposium on Parallelism in Algorithms and Architectures
(SPAA), Revue Session, June 2003. (pdf)
- Periodicals:
- J. F. Cantin and M. D. Hill, "Cache Performance for Selected SPEC CPU2000
Benchmarks", Computer Architecture News, Vol. 29, No. 4 -September 2001.
(online)
- J. F. Cantin, A. Moshovos, M. H. Lipasti, J. E. Smith, and B. Falsafi, "Coarse-Grain
Coherence Tracking: RegionScout and Region Coherence Arrays", IEEE Micro
Special Issue on Top Picks from 2005 Computer Architecture Conferences,
Jan-Feb 2006. (online)
- Issued Patents:
- #6,960,941: Latch Circuit Capable of Ensuring Race-Free Staging for Signals in
Dynamic Logic Circuits. Assigned to International Business Machines, 2004.
- #6,107,839: A High Input Impedance, Strobed CMOS Differential Sense Amplifier
with Double Fire Evaluate. Assigned to Compaq Computer Corporation, 2000.
- Filed Patents:
- Data Processing System and Method for Efficient Communication Utilizing an In
Coherency State. Filed by International Business Machines, 2005.
- Method, Apparatus, and Computer Program Product for a Cache Coherency
Protocol State that Predicts Locations of Shared Memory Blocks. Filed
by International Business Machines, 2005.
- Method, Apparatus, and Computer Program Product for a Cache Coherency
Protocol State that Predicts Locations of Modified Memory Blocks. Filed
by International Business Machines, 2005.
- Theses:
- "The Complexity of Verifying Memory Coherence", MS Thesis, December 2002
(pdf)
- "Coarse-Grain Coherence Tracking", PhD Thesis, Summer 2006
(pdf)
Last updated February, 2008.