CASPR stands for Configurable Architecture for Smart Pixel Research, and was a project started at the University of Cincinnati with the goal of expediting smart pixel application development. The original focus of the project was to build a smart pixel system based on concepts from early parallel computers. Optical receivers and simple processors could be integrated into cells, aggregated into a large array, and controlled via a SIMD programming model. In theory, one could then emulate any photonic information processing system with software. Further, multiple chips could be interconnected to form very large 2-dimensional arrays.
In the Winter of 2000, a proof-of-concept design was created by Jason F. Cantin and Fred R. Beyette in the Photonic Systems Development Laboratory (PSDL). This design consisted of a 2x2 array of bit-sliced processors that were each equipped with a BJT-based photodetector. In addition, a control-store located on chip was included so that the instruction set understood by the processors could be changed dynamically to meet application needs (while still supporting a dense encoding of instructions). The design was fabricated via the MOSIS service with 1.2-micron rules in AMI's Mixed Signal Process (2 metal layers, 2 polysilicon). First-silicon was received the following Spring.
As with any major project, mistakes were made and problems were encountered. The prototype implementation was unnecessarily complicated, and the ability to redefine the instruction set did not prove useful. In addition, the fabrication facility was unable to guarantee consistent electrical behavior for the manufacturing process at that time (leading to some peculiar effects). Finally, the prototype was designed and fabricated before a host computer was available, and little application development had been done to test the programming model. These lessons are driving the design of a simplified and more powerful implementation of CASPR.
The notable thing about CASPR is the idea that an entire processor CAN be incorporated into a pixel AND programmed generically. With modern CMOS technology, a bit-sliced processor can be made comparable in size to a photodetector. The flexibility and programming ease of a SIMD array is not an impractical goal. Thus, the need for exotic image processing architectures with separate chips for receiving data is questionable.